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FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
May 2001
FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
General Description
The FM27C512 is a high performance 512K UV Erasable Electrically Programmable Read Only Memory (EPROM). It is manufactured using Fairchild's proprietary CMOS AMGTM EPROM technology for an excellent combination of speed and economy while providing excellent reliability. The FM27C512 provides microprocessor-based systems storage capacity for portions of operating system and application software. Its 90 ns access time provides no wait-state operation with high-performance CPUs. The FM27C512 offers a single chip solution for the code storage requirements of 100% firmwarebased equipment. Frequently-used software routines are quickly executed from EPROM storage, greatly enhancing system utility. The FM27C512 is configured in the standard JEDEC EPROM pinout which provides an easy upgrade path for systems which are currently using standard EPROMs. The FM27C512 is one member of a high density EPROM Family which range in densities up to 4 Megabit.
Features
I High performance CMOS -- 90, 120, 150 ns access time I Fast turn-off for microprocessor compatibility I Manufacturers identification code I JEDEC standard pin configuration -- 32-pin PLCC package -- 28-pin CERDIP package
Block Diagram
VCC GND VPP OE CE/PGM Output Enable and Chip Enable Logic Output Buffers Data Outputs O0 - O7
Y Decoder
..
524,288-Bit Cell Matrix
A0 - A15 Address Inputs
.......
X Decoder
DS800035-1 AMG is a trademark of WSI, Inc.
(c) 2001 Fairchild Semiconductor Corporation FM27C512 Rev. A
1
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FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Connection Diagrams
27C040 27C010 27C256 XX/VPP XX/VPP A16 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
DIP FM27C512
A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A14 A13 A8 A9 A11 OE/VPP A10 CE/PGM O7 O6 O5 O4 O3
27C256 27C010 27C040 VCC VCC A14 A13 A8 A9 A11 OE A10 CE/PGM O7 O6 O5 O4 O3 XX/PGM XX A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3 VCC A18 A17 A14 A13 A8 A9 A11 OE A10 CE/PGM O7 O6 O5 O4 O3
VPP
A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND
DS800035-2
Compatible EPROM pin configurations are shown in the blocks adjacement to the FM27C512 pins.
Commercial Temp Range (0C to +70C)
Parameter/Order Number
FM27C512 Q, V 90 FM27C512 Q, V 120 FM27C512 Q, V 150
Pin Names
A0-A15 CE/PGM OE O0-O7 NC Addresses Chip Enable/Program Output Enable Outputs Don't Care (During Read)
Access Time (ns)
90 120 150
Industrial Temp Range (-40C to +85C)
PLCC
FM27C512 QE, VE 90 FM27C512 QE, VE 120 FM27C512 QE, VE 150 Q = Quartz-Windowed Ceramic DIP Package V = PLCC Package * All packages conform to the JEDEC standard. * All versions are guaranteed to function for slower speeds. 90 120 150
A6 A5 A4 A3 A2 A1 A0 NC O0 5 6 7 8 9 10 11 12 13
14 15 16 17 18 19 20
A7 A12 A15 NC VCC A14 A13
4 3 2 1 32 31 30
Parameter/Order Number
Access Time (ns)
29 28 27 26 25 24 23 22 21
A8 A9 A11 NC OE/VPP A10 CE/PGM O7 O8
O1 O2 GND NC O3 O4 O5
DS800035-3
2
FM27C512 Rev. A
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FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Absolute Maximum Ratings (Note 1)
Storage Temperature All Input Voltages Except A9 with Respect to Ground VPP and A9 with Respect to Ground VCC Supply Voltage with Respect to Ground -65C to +150C -0.6V to +7V -0.7V to +14V -0.6V to +7V
ESD Protection (MIL Std. 883, Method 3015.2) All Output Voltages with Respect to Ground
>2000V VCC + 1.0V to GND -0.6V
Operating Range
Range
Commercial Industrial
Temperature
0C to +70C -40C to +85C
VCC
+5V +5V
Tolerance
10% 10%
Read Operation DC Electrical Characteristics
Symbol
VIL VIH VOL VOH ISB1 ISB2 ICC1 ICC2
Parameter
Input Low Level Input High Level Output Low Voltage Output High Voltage VCC Standby Current (CMOS) VCC Standby Current VCC Active Current VCC Active Current CMOS Inputs VPP Supply Current VPP Read Voltage Input Load Current Output Leakage Current
Test Conditions
Min
-0.5 2.0
Max
0.8 VCC +1 0.4
Units
V V V V
IOL = 2.1 mA IOH = -2.5 mA CE = VCC 0.3V CE = VIH CE = OE = VIL f = 5 MHz 3.5
100 1 40 35 10 VCC - 0.7 VCC 1 10
A mA mA mA A V A A
CE = GND, f = 5 MHz Inputs = VCC or GND, I/O = 0 mA C, E Temp Ranges VPP = VCC
IPP VPP ILI ILO
VIN = 5.5V or GND VOUT = 5.5V or GND
-1 -10
AC Electrical Characteristics
Symbol
tACC tCE tOE tDF tOH
Parameter Min
Address to Output Delay CE to Output Delay OE to Output Delay Output Disable to Output Float Output Hold from Addresses, CE or OE, Whichever Occurred First 0
90 Max
90 90 40 35 0
Min
120 Max
120 120 50 25
150 Min Max
150 150 50 45 0
Units
ns
3
FM27C512 Rev. A
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FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Capacitance TA = +25C, f = 1 MHz (Note 2)
Symbol
CIN1 COUT CIN2
Parameter
Input Capacitance except OE/VPP Output Capacitance OE/VPP Input Capacitance
Conditions
VIN = 0V VOUT = 0V VIN = 0V
Typ
6 9 20
Max
12 12 25
Units
pF pF pF
AC Test Conditions
Output Load 1 TTL Gate and CL = 100 pF (Note 8) 5 ns 0.45V to 2.4V 0.8V and 2V 0.8V and 2V Input Rise and Fall Times Input Pulse Levels Timing Measurement Reference Level (Note 9) Inputs Outputs
AC Waveforms (Notes 6, 7)
ADDRESS
2V 0.8V
Address Valid
CE
2V 0.8V
t CF
(Note 4, 5)
OE
2V 0.8V
t CE t OE
(Note 3)
t DF
(Note 4, 5)
Valid Output
OUTPUT
2V 0.8V
Hi-Z t ACC
(Note 3)
Hi-Z t OH
DS800035-4
Note 1: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: This parameter is only sampled and is not 100% tested. Note 3: OE may be delayed up to tACC -tOE after the falling edge of CE without impacting tACC. Note 4: The tDF and tCF compare level is determined as follows: High to TRI-STATE, the measured VOH1 (DC) - 0.10V; Low to TRI-STATE, the measured VOL1 (DC) + 0.10V. Note 5: TRI-STATE may be attained using OE or CE . Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 F ceramic capacitor be used on every device between VCC and GND. Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage. Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 A. CL: 100 pF includes fixture capacitance. Note 9: Inputs and outputs can undershoot to -2.0V for 20 ns Max.
4
FM27C512 Rev. A
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FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Programming Characteristics (Note 10) and (Note 11)
Symbol
tAS tOES tDS tVCS tAH tDH tCF tPW tOEH tDV tPRT tVR IPP ICC TR VCC VPP tFR VIL VIH tIN tOUT
Parameter
Address Setup Time OE Setup Time Data Setup Time VCC Setup Time Address Hold Time Data Hold Time Chip Enable to Output Float Delay Program Pulse Width OE Hold Time Data Valid from CE OE Pulse Rise Time during Programming VPP Recovery Time VPP Supply Current during Programming Pulse VCC Supply Current Temperature Ambient Power Supply Voltage Programming Supply Voltage Input Rise, Fall Time Input Low Voltage Input High Voltage Input Timing Reference Voltage Output Timing Reference Voltage
Conditions
Min
1 1 1 1 0 1
Typ
Max
Units
s s s s s s
OE = VIL
0 45 1 50
60 105
ns s s
OE = VIL 50 1 CE = VIL OE = VPP
250
ns ns s
30 50 20 6.25 12.5 5 0 2.4 0.8 0.8 4 2 2 0.45 25 6.5 12.75 30 6.75 13
mA mA C V V ns V V V V
Programming Waveforms
Program Addresses 2.0V 0.8V t AS 2.0V Data 0.8V t DS 12.75V 0.8V tPRT CE/PGM t OES t VPS t VCS 6.25V t OEH t VR Data In Stable ADD N t DH Hi-Z 2.0V 0.8V t DV Data Out Valid ADD N t CF t AH Address N Program Verify
OE/VPP
t PW
VCC
DS800035-5
Note 10: Fairchild's standard product warranty applies to devices programmed to specifications described herein. Note 11: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. The EPROM must not be inserted into or removed from a board with voltage applied to VPP or VCC. Note 12: The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V. Care must be taken when switching the VPP supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 F capacitor is required across VCC to GND to suppress spurious voltage transients which may damage the device.
5
FM27C512 Rev. A
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FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Turbo Programming Algorithm Flow Chart
VCC = 6.5V VPP = 12.75V n=0 ADDRESS = FIRST LOCATION
PROGRAM ONE 50s PULSE INCREMENT n
NO
DEVICE FAILED
YES
n = 10?
FAIL
VERIFY BYTE
PASS
LAST ADDRESS ?
YES
NO
INCREMENT ADDRESS n=0
ADDRESS = FIRST LOCATION
VERIFY BYTE INCREMENT ADDRESS
NO PASS
FAIL
PROGRAM ONE 50 s PULSE
LAST ADDRESS ?
YES
CHECK ALL BYTES 1ST: VCC = VPP = 6.0V 2ND: VCC = VPP = 4.3V
Note: The standard National Semiconductor algorithm may also be used but it will take longer programming time. DS800035-6
FIGURE 1.
6
FM27C512 Rev. A
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FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Functional Description
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Table1. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are VCC and OE/VPP. The OE/VPP power supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The VCC power supply must be at 6.5V during the three programming modes, and at 5V in the other three modes.
The EPROM is in the programming mode when the OE/VPP is at 12.75V. It is required that at least a 0.1 F capacitor be placed across VCC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, an active low, TTL program pulse is applied to the CE/PGM input. A program pulse must be applied at each address location to be programmed. The EPROM is programmed with the Turbo Programming Algorithm shown in Figure 1. Each Address is programmed with a series of 50 s pulses until it verifies good, up to a maximum of 10 pulses. Most memory cells will program with a single 50 s pulse. (The standard National Semiconductor Algorithm may also be used but it will have longer programming time.) The EPROM must not be programmed with a DC signal applied to the CE/PGM input. Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied to the CE/PGM input programs the paralleled EPROM.
Read Mode
The EPROM has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE/PGM) is the power control and should be used for device selection. Output Enable (OE/VPP) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tACC - tOE.
Standby Mode
The EPROM has a standby mode which reduces the active power dissipation by over 99%, from 220 mW to 0.55 mW. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE/PGM input. When in standby mode, the outputs are in a high impedance state, independent of the OE input.
Program Inhibit
Programming multiple EPROMs in parallel with different data is also easily accomplished. Except for CE/PGM all like inputs (including OE/VPP) of the parallel EPROMs may be common. A TTL low level program pulse applied to an EPROM's CE/PGM input with OE/VPP at 12.75V will program that EPROM. A TTL high level CE/PGM input inhibits the other EPROMs from being programmed.
Output Disable
The EPROM is placed in output disable by applying a TTL high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRISTATE).
Program Verify
A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify is accomplished with OE/VPP and CE at VIL. Data should be verified TDV after the falling edge of CE.
Output OR-Typing
Because the EPROM is usually used in larger memory arrays, Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recommended that CE/PGM be decoded and used as the primary device selecting function, while OE/VPP be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device.
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents.
MANUFACTURER'S IDENTIFICATION CODE
The EPROM has a manufacturer's identification code to aid in programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code. The Manufacturer's Identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for FM27C512 is "8F85", where "8F" designates that it is made by Fairchild Semiconductor, and "85" designates a 512K part. The code is accessed by applying 12V 0.5V to address pin A9. Addresses A1-A8, A10-A16, and all control pins
Programming
CAUTION: Exceeding 14V on pin 22 (OE/VPP) will damage the EPROM. Initially, and after each erasure, all bits of the EPROM are in the "1's" state. Data is introduced by selectively programming "0's" into the desired bit locations. Although only "0's" will be programmed, both "1's" and "0's" can be presented in the data word. The only way to change a "0" to a "1" is by ultraviolet light erasure.
7
FM27C512 Rev. A
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FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Functional Description (Continued)
are held at VIL. Address pin A0 is held at VIL for the manufacturer's code, and held at VIH for the device code. The code is read on the eight data pins, O0 -O 7 . Proper code access is only guaranteed at 25C 5C.
Lamps lose intensity as they age. When a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem.
ERASURE CHARACTERISTICS
The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000A-4000A range. The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537A. The integrated dose (i.e., UV intensity x exposure time) for erasure should be minimum of 15W-sec/cm2. The EPROM should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure An erasure system should be calibrated periodically. The distance from lamp to device should be maintained at one inch. The erasure time increases as the square of the distance from the lamp (if distance is doubled the erasure time increases by factor of 4).
SYSTEM CONSIDERATION
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. The associated VCC transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 F ceramic capacitor be used on every device between VCC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 F bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces.
Mode Selection
The modes of operation of the FM27C512 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels excepts for VPP and A9 for device signature.
TABLE 1. Mode Selection Pins Mode
Read Output Disable Standby Programming Program Verify Program Inhibit
Note 13: X can be VIL or VIH.
CE/PGM
VIL X (Note 13) VIH VIL VIL VIH
OE/VPP
VIL VIH X 12.75V VIL 12.75V
VCC
5.0V 5.0V 5.0V 6.25V 6.25V 6.25V
Outputs
DOUT High Z High Z DIN DOUT High Z
TABLE 2. Manufacturer's Identification Code Pins
Manufacturer Code Device Code
A0 (10)
VIL VIH
A9 (24)
12V 12V
07 (19)
1 1
06 (18)
0 0
05 (17)
0 0
04 (16)
0 0
03 (15)
1 0
02 (13)
1 1
01 (12)
1 0
00 (11)
1 1
Hex Data
8F 85
8
FM27C512 Rev. A
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FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
1.465 MAX [37.211] 28 15
R 0.025 [0.635] 0.515-0.530 [13.081-13.462]
R 0.030-0.055 [0.762-1.397] TYP
1 0.290-0.310 [7.366-7.874] U.V. WINDOW 0.050-0.060 [1.270-1.524] TYP GLASS SEALANT
14
0.010 [0.254] MAX 0.180 [4.572] MAX
0.590-0.620 [14.99-15.75]
0.225 [5.715] MAX TYP
0.125 [3.175] MIN TYP 0.060-0.100 [1.524-2.540] TYP 0.090-0.110 [2.286-2.794] TYP
86-94 TYP 0.015-0.021 [0.381-0.533] TYP 0.033-0.045 [0.838-1.143] TYP 0.015-0.060 [0.381-1.524] TYP
90-100 TYP 0.008-0.012 [0.203-0.305] TYP +0.025 0.685 -0.060 +0.635 [17.399 -1.524 ]
UV Window Cavity Dual-In-Line Cerdip Package (JQ) Order Number FM27C512Q Package Number J28CQ
9
FM27C512 Rev. A
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FM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.485-0.495 [12.32-12.57]
0.007[0.18] S B D-E S
0.449-0.453 [11.40-11.51] -A0.045 [1.143] 0.000-0.010 [0.00-0.25] Polished Optional
0.106-0.112 [2.69-2.84] 0.023-0.029 [0.58-0.74]
-H-
Base Plane
0.015 [0.38] Min Typ
0.007[0.18] S B D-E S 0.002[0.05] S B -D4 5 1 30 29 0.541-0.545 [13.74-13-84]
60
( [10.16] )
0.400
0.490-0530 [12.45-13.46] 0.015[0.38] S C D-E, F-G S
0.549-0.553 [13.94-14.05] -B0.585-0.595 [14.86-15.11]
-G-
-FSee detail A -J13 14
0.002[0.05] S A 0.007[0.18] S A F-G S
0.013-0.021 TYP [0.33-0.53] 0.007[0.18] M 0.078-0.095 [1.98-2.41] -C0.004[0.10] 0.020 [0.51] 0.005 Max [0.13] 0.0100 [0.254] C D-E, F-G S
21 20 -E-
0.007[0.18] S
A F-G S
0.118-0.129 [3.00-3.28] 0.010[0.25] L B A D-E, F-G S B 0.042-0.048 45X [1.07-1.22]
B
0.026-0.032 Typ [0.66-0.81]
0.007[0.18] S H D-E, F-G S
; ;
0.025 [0.64] Min 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64]
0.050
0.123-0.140 [3.12-3.56]
0.045 [1.14] 0.025 [0.64] Min 0.021-0.027 [0.53-0.69]
Detail A Typical Rotated 90
R
0.030-0.040 [0.76-1.02]
0.065-0.071 [1.65-1.80]
0.053-0.059 [1.65-1.80] 0.031-0.037 [0.79-0.94] 0.027-0.033 [0.69-0.84]
Section B-B Typical
32-Lead Plastic Leaded Chip Carrier (PLCC) Order Number FM27C512V Package Number VA32A
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383
Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
10
FM27C512 Rev. A
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